Particle performance is of concern in processing semiconductor substrates such as silicon wafers due to reduction in yield caused by particles adhered to the surface of such substrates. One source of such particles is the substrates and techniques for reducing the number of particles include chemical treatments. For instance, U.S. Pat. No. 5,051,134 discloses a wet chemical treatment for reducing the number of particles by treating a semiconductor surface with an aqueous solution containing hydrofluoric acid. The '134 patent states that the acid solution includes commercially available hydrofluoric acid and water which meet the exceptionally high purity and particle freedom requirements of the semiconductor industry.
U.S. Pat. No. 5,665,168 discloses a method for cleaning a silicon wafer so as to suppress and reduce adhesion of particles to the surface of the wafer wherein the wafer is cleaned with a hydrofluoric acid aqueous solution containing a surfactant followed by rinsing the wafer with pure water containing ozone. U.S. Pat. No. 5,837,662 discloses a process for cleaning contaminants from the surface of a wafer after the wafer has been lapped, the process including contacting the wafer with an oxidizing agent to oxidize organic contaminants and immersing the wafer in an aqueous bath containing citric acid into which sonic energy is directed to remove metallic contaminants present on the surface of the wafer. The '662 patent states that the citric acid is a complexing agent which serves to trap metal ions and that particles of lapping grit and trace metallic impurities present in a layer of silicon oxide (which is part native oxide and partly formed in the oxidizing bath) can be removed along with the oxide layer by contacting the wafer with hydrofluoric acid.
U.S. Pat. No. 5,712,198 discloses a technique for treating silicon wafers to reduce the concentration of metals such as Cr, Ca, Ti, Co, Mn, Zn and V on the surface thereof, the process including precleaning with a cleaning solution, metals removal with an aqueous solution containing HF, rinsing and oxide growth to produce a silicon oxide layer with a thickness of 0.6 to 1.5 nanometers by contacting the wafers with high purity ozonated water having a concentration of no more than 0.01 parts per billion each of Fe, Cr, Ti and other metals. Other patents which relate to cleaning of semiconductor substrates include U.S. Pat. Nos. 5,454,901; 5,744,401; and 6,054,373.
U.S. Pat. No. 5,766,684 discloses a technique for cleaning and passivating stainless steel surfaces such as gas flow equipment which can be used in semiconductor processing equipment, the process including contacting the surfaces with an aqueous solution containing acid so as to dislodge and remove residue followed by complexing free Fe ions liberated from the surface to form an oxide film and precipitating the complexed ions into the oxide film.
U.S. Pat. No. 4,761,134 discloses silicon carbide components (e.g., liners, process tubes, paddles, boats, etc.) for semiconductor diffusion furnaces used to process silicon wafers wherein high purity silicon carbide components are impregnated with high purity silicon metal and coated with a high purity dense, impervious refractory coating such as silicon carbide, silicon nitride or silicon dioxide. According to the '134 patent, the silicon carbide must be at least 99% pure (preferably at least 99.9% pure) so as not to be a source of contamination to the furnace environment during sensitive wafer processing steps and the refractory coating protects the silicon impregnated sintered silicon carbide substrate from exposure to the furnace environment and attack by acid during acid cleaning. Other patents relating to silicon carbide semiconductor processing components include U.S. Pat. No. 4,401,689 (susceptor tube), U.S. Pat. No. 4,518,349 (furnace support rod), U.S. Pat. No. 4,999,228 (diffusion tube), U.S. Pat. No. 5,074,456 (upper electrode), U.S. Pat. No. 5,252,892 (plasma cathode chamber), U.S. Pat. No. 5,460,684 (resistive layer of ESC), U.S. Pat. No. 5,463,524 (sensing pin), U.S. Pat. No. 5,494,524 (heat treatment device), U.S. Pat. No. 5,578,129 (filter plate of load lock system), U.S. Pat. No. 5,538,230 (wafer boat), U.S. Pat. No. 5,595,627 (upper electrode), U.S. Pat. No. 5,888,907 (electrode plate), U.S. Pat. No. 5,892,236 (ion implantation device) and U.S. Pat. No. 5,937,316 (heat treatment device such as susceptor, wafer holder, thermal uniformity plate, thermal uniformity ring, dummy wafer). See also, Japanese Patent Publication Nos. 54-10825 (semiconductor diffusion oven material), 60-200519 (susceptor), 61-284301 (upper electrode), 63-35452 (diffusion oven tube, liner tube, port element, paddle), 63-186874 (microwave heated sample plate), 63-138737 (upper electrode of plasma (wafer heater). Of these, Japanese Patent Publication Nos. 54-10825 and 63-35452 disclose parts made of slip cast silicon carbide.
U.S. Pat. No. 4,598,665 discloses a technique for reducing dust during heat treatment of semiconductor wafers by providing a silicon carbide process tube (wherein the wafers are treated) with an inner surface coarseness of 150 μm or less. The '665 patent states that when the surface coarseness is greater than 150 μm, a porous SiO2 film is formed on the inner surface of the process tube leading to dust generation.
U.S. Pat. No. 5,904,778 discloses a SiC CVD coating on free standing SiC for use as a chamber wall, chamber roof, or collar around the wafer. U.S. Pat. No. 5,292,399 discloses a SiC ring surrounding a wafer pedestal. A technique for preparing sintered SiC is disclosed in U.S. Pat. No. 5,182,059.
With regard to plasma reactor components such as showerhead gas distribution systems, various proposals have been made with respect to the materials of the showerheads. For instance, U.S. Pat. No. 5,569,356 discloses a showerhead of silicon, graphite, or silicon carbide. U.S. Pat. No. 5,888,907 discloses a showerhead electrode of amorphous carbon, SiC or Al. U.S. Pat. Nos. 5,006,220 and 5,022,979 disclose a showerhead electrode either made entirely of SiC or a base of carbon coated with SiC deposited by CVD to provide a surface layer of highly pure SiC.
In view of the need for increased yield during semiconductor processing, there is a need in the art for improvements in reduction of particles caused by shaped (e.g., machined and/or sintered) ceramic parts exposed to the gases and/or the environment in which the semiconductor substrates are processed.